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MDT10P62
1. General Description
This EPROM-Based 8-bit micro-controller uses a fully static CMOS technology process to achieve higher speed and smaller size with the low power consumption and high noise immunity. On chip memory includes 2K words of ROM, and 128 bytes of static RAM. u u TMR0 : 8-bit real time clock/counter TMR1 : 16-bit real time clock/count TMR2 : 8-bit clock/counter(internal) 4 types of oscillator can be selected by programming option: -PortB<7:4> interrupt on change -CCP,SCM
2. Features
The followings are some of the features on the hardware and software : u u u u Fully CMOS static design 8-bit data bus On chip EPROM size : 2.0 K words Internal RAM size : 160 bytes (128 general purpose registers, 32 special registers) u u u u 37 single word instructions 14-bit instructions 8-level stacks Operating voltage : 2.5 V ~ 5.5 V (PRD Disable) 4.5 V ~ 5.5 V (PRD Enable) u u Operating frequency : DC ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u u u u u u u Power-on Reset Power edge-detector Reset Power range-detector Reset Sleep Mode for power saving Capture,Compare,PWM module Synchronous serial port with SCM 7 interrupt sources: -External INT pin -TMR0 timer,TMR1 timer,TMR2 timer u u
RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator On-chip RC oscillator based Watchdog Timer(WDT) 22 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT10P62 range from appliance motor control and high speed auto-motive to low power remote transmitters/receivers, pointing
devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
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P.1
2005/6 Ver2.0
MDT10P62
4. Pin Assignment /MCLR PA0 PA1 PA2 PA3 PA4/RTCC PA5/SS Vss OSC1/CLKIN OSC2/CLKOUT PC0/T1OSO/T1CKI PC1/T1OSI PC2/CCP PC3/SCK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0/INT Vdd Vss PC7 PC6 PC5/SDO PC4/SDI
5. Pin Function Description
Pin Name PA0~PA3,PA5 RTCC/PA4 I/O I/O I/O Port A, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Open drain output PB0~PB7 I/O Port B, TTL input level / PB0:External interrupt input , PB4~PB7:Interrupt on pin change PC0~PC7 /MCLR OSC1/CLKIN OSC2/CLKOUT I/O I I O Port C, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input/external clock input Oscillator Output/in RC modeA the CLKOUT pin has 1/4 frequency of CLKIN Vdd Vss Power supply Ground Function Description
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P.2
2005/6 Ver2.0
MDT10P62
6. Memory Map
(A) Register Map
Address BANK0 00 01 02 03 04 05 06 07 0A 0B 0C 0E 0F 10 11 12 13 14 15 16 17 20~7F BANK1 01 05 06 07 0C TMR CPIO A CPIO B CPIO C PIEB1
Description
Indirect Addressing Register RTCC PCL STATUS MSR Port A Port B Port C PCHLAT INTS PIFB1 TMR1L TMR1H T1STA TMR2 T2STA SCMBUF SCMCTL CCPL CCPH CCPCTL General purpose register
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P.3
2005/5
Ver. 1.9
MDT10P62
Address 0E 12 14 A0~BF PSTA T2PER SCMSTA General purpose register Description
(1)IAR ( Indirect Address Register) : R00 (2)RTCC (Real Time Counter/Counter Register) : R01 (3) PC (Program Counter) : R02,R0A Write PC --- from PCHLAT Write PC --- from PCHLAT LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A11
A10~A8
A7~A0
Write PC --- from ALU LJUMP, LCALL --- from instruction word RTWI, RET, RTFI --- from STACK (4) STATUS (Status register) : R03
Bit
0 1 2 3 4 5
Symbol
C HC Z PF TF RBS0 Carry bit Half Carry bit Zero bit
Function
Power down Flag bit WDT Timer overflow Flag bit Register Bank Select bit : 0 : 00H --- 7FH (Bank0) 1 : 80H --- FFH (Bank1)
6-7
XX
General purpose bit
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P.4
2005/5
Ver. 1.9
MDT10P62
(5) MSR (Memory Bank Select Register) : R04 Memory Bank Select Register : 0 : 00~7F (Bank0) 1 : 80~FF (Bank1)
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode (6) PORT A : R05 PA5~PA0, I/O Register (7) PORT B : R06 PB7~PB0, I/O Register (8) PORT C : R07 PC7~PC0, I/O Register (9)PCHLAT : R0A
(10) INTS ( Interrupt Status Register ) : R0B Bit 0 1 2 3 Symbol RBIF INTF TIF RBIE Function PORT B change interrupt flag. Set when PB <7:4> inputs change Set when INT interrupt occurs. INT interrupt flag. Set when TMR0 overflows. 0 : disable PB change interrupt 1 : enable PB change interrupt 4 INTS 0 : disable INT interrupt 1 : enable INT interrupt 5 TIS 0 : disable TMR0 interrupt 1 : enable TMR0 interrupt 6 PEIE 0 : disable all peripheral interrupt 1 : enable all peripheral interrupt 7 GIS 0 : disable global interrupt 1 : enable global interrupt
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P.5
2005/5
Ver. 1.9
MDT10P62
(11)PIFB1 (Peripheral Interrupt Flag Bit) : R0C Bit 0 Symbol TMR1IF TMR1 interrupt flag 0 : TMR1 did not overflow 1 : TMR1 overflowed 1 TMR2IF TMR2 interrupt flag 0 : No TMR2 to T2PER match occurred 1 : TMR2 to T2PER match occurred 2 CCPIF CCP interrupt flag 0 : No TMR1 capture/compare occurred 1 : A TMR1 capture/compare occurred 3 SCMIF SCM interrupt flag 0 : Waiting SCM transmit/receive 1 : The SCM transmission/reception is complete 7~4 -Unimplemented Function
(12) TMR1L : R0E The LSB of the 16-bit TMR1
(13) TMR1H : R0F The MSB of the 16-bit TMR1
(14) T1STA : R10 Bit 0 Symbol TMR1ON 0 : Stop TMR1 1 : enable TMR1 1 TMR1CLK 0 : Internal clock (Fosc/4) 1 : External clock from pin PC0 2 /T1SYNC TMR1CLK = 1 0 : Synchronize external clock 1 : Do not synchronize external clock TMR1CLK = 0 This bit is ignored 3 T1OSCEN 0 : TMR1 Oscillator is shut off 1 : TMR1 Oscillator is enable Function
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P.6
2005/5
Ver. 1.9
MDT10P62
Bit 5~4 Symbol T1CKPS1 ~ T1CKPS0 1 1 = 1:8 Prescale value 1 0 = 1:4 Prescale value 0 1 = 1:2 Prescale value 0 0 = 1:1 Prescale value 7~6 -Unimplemented Function
(15) TMR2 : R11 TMR2 register
(16) T2STA : R12
Bit 1~0
Symbol T2CKPS1 ~ T2CKPS0 0 0 = Prescaler is 1 0 1 = Prescaler is 4 1 x = Prescaler is 16 0 : TMR2 is on 1 : TMR2 is off
Function
2
TMR2ON
7~3
--
Unimplemented
(17) SCMBUF : R13 Serial communication port buffer
(18) SCMCTL : R14 Bit 3~0 Symbol SCM3 ~ SCM0 Function 0 0 0 0 : SCM master mode , clock = Fosc/4 0 0 0 1 : SCM master mode , clock = Fosc/16 0 0 1 0 : SCM master mode , clock = Fosc/64 0 0 1 1 : SCM master mode , clock = TMR2 output/2 0 1 0 0 : SCM slave mode , clock = SCK pin , /SS control enable 0 1 0 1 : SCM slave mode , clock = SCK pin , /SS control disable 4 CKS 0 : Transmit happens on rising edge , receive on falling edge, Idle state for clock is low level 1 : Transmit happens on falling edge , receive on rising edge, Idle state for clock is high level.
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P.7
2005/5
Ver. 1.9
MDT10P62
Bit 5 Symbol SCMEN Function 0 : disable SCM, then pc3, pc4, pc5 is I/O port 1 : enable SCM 6 SCMROI 0 : No overflow 1 : Overflow 7 WCOL 0 : No collision 1 : The SCMBUF is written while it is still transmitting the previous word
(19) CCPL : R15 Capture/Compare/PWM LSB
(20) CCPH : R16 Capture/Compare/PWM MSB
(21) CCPCTL : R17
Bit 3~0
Symbol CCPM3 ~ CCPM0 0 0 0 0 : CCP off
Function
0 1 0 0 : Capture mode , every falling edge 0 1 0 1 : Capture mode , every rising edge 0 1 1 0 : Capture mode , every 4th rising edge 0 1 1 1 : Capture mode , every 16th rising edge 1 0 0 0 : Compare mode , set output on match 1 0 0 1 : Compare mode , clear output on match 1 0 1 0 : Compare mode , generate software interrupt on match 1 0 1 1 : Compare mode , trigger special event 1 1 x x : PWM mode
5~4 7~6
PWMLSB --
These bits are the two LSBs of the PWM duty cycle Unimplemented
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P.8
2005/5
Ver. 1.9
MDT10P62
(22) TMR (Time Mode Register) : R81 Bit Symbol Prescaler Value 000 001 010 011 2~0 PS2~0 100 101 110 Function RTCC rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 WDT rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
111 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin Interrupt edge select 0 X Interrupt on falling edge on PB0 1 X Interrupt on rising edge on PB0 PORTB pull-hi 0 X PORTB pull-hi are enable 1 X PORTB pull-hi are disable
(23) CPIO A (Control Port I/O Mode Register) : R85 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (24) CPIO B (Control Port I/O Mode Register) : R86 x"0", I/O pin in output mode; x"1", I/O pin in input mode. (25) CPIO C (Control Port I/O Mode Register) : R87 x"0", I/O pin in output mode; x"1", I/O pin in input mode.
(26) PIEB1 : R8C Bit 0 Symbol TMR1IE TMR1 interrupt enable bit 0 : disable TMR1 interrupt 1 : enable TMR1 interrupt Function
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P.9
2005/5
Ver. 1.9
MDT10P62
Bit 1 Symbol TMR2IE TMR2 interrupt enable bit 0 : disable TMR2 interrupt 1 : enable TMR2 interrupt 2 CCPIE CCP interrupt enable bit 0 : disable CCP interrupt 1 : enable CCP interrupt 3 SCMIE SCM interrupt enable bit 0 : disable SCM interrupt 1 : enable SCM interrupt 7~4 (27) PSTA : R8E Bit 0 1 Symbol PRDB PORB 0:Power range-detector Reset occurred 1:No Power range-detector Reset Occurred 0:Power on Reset occurred 1:No Power on Reset occurred (28) T2PER : R92 Timer2 period (29) SCMSTA : R94 Bit 0 Symbol BF 0 : Receive not complete 1 : Receive complete 7~1 -Unimplemented Function Function -Unimplemented Function
(30) Configurable options for EPROM (Set by writer) :
Oscillator Type RC Oscillator
HFXT Oscillator XTAL Oscillator LFXT Oscillator
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P.10
2005/5
Ver. 1.9
MDT10P62
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
Power-range control Power-range disable Power-range enable
Oscillator-start Timer control 0ms 75ms
Power-edge Detect PED Disable PED Enable (B) Program Memory
Security state Security Disable Security Enable
Address 000-7FF 000 004 Program memory
Description
The starting address of power on, external reset or WDT time-out reset. Interrupt vector
7. Reset Condition for all Registers
Register Address Power-On Reset, Power range detector Reset IAR RTCC PC STATUS MSR PORT A PORT B 00h 01h 0Ah,02h 03h 04h 05h 06h N/A xxxx xxxx 0000 0000 0000 0001 1xxx xxxx xxxx --xx xxxx xxxx xxxx N/A uuuu uuuu 0000 0000 0000 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu N/A uuuu uuuu PC+1 000# #uuu uuuu uuuu --uu uuuu uuuu uuuu /MCLR or WDT Reset Wake-up from SLEEP
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P.11
2005/5
Ver. 1.9
MDT10P62
Register Address Power-On Reset, Power range detector Reset PORT C PCHLAT INTS PIFB1 TMR1L TMR1H T1STA TMR2 T2STA SCMBUF SCMCTL CCPL CCPH CCPCTL TMR CPIOA CPIOB CPIOC PIEB1 PSTA T2PER SCMSTA 07h 0Ah 0Bh 0Ch 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 81h 85h 86h 87h 8Ch 8Eh 92h 94h xxxx xxxx ---0 0000 0000 000x ---- 0000 xxxx xxxx xxxx xxxx --00 0000 0000 0000 ---- -000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 1111 1111 --11 1111 1111 1111 1111 1111 ---- 0000 ---- --0u 1111 1111 ---- ---0 uuuu uuuu ---0 0000 0000 000u ---- 0000 uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 ---- -uuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 1111 1111 --11 1111 1111 1111 1111 1111 ---- 0000 ---- --uu 1111 1111 ---- ---0 uuuu uuuu ---u uuuu uuuu uuuu ---- uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- --uu 1111 1111 ---- ---u /MCLR or WDT Reset Wake-up from SLEEP
Note : uxunchanged, xxunknown, -xunimplemented, read as "0" #xvalue depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Power-on reset Power-range reset Status: bit 4 u 1 0 0 1 1 Status: bit 3 u 0 1 0 1 1 PSTA: bit 1 u u u u 0 u PSTA: bit 0 u u u u x 0
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P.12
2005/5
Ver. 1.9
MDT10P62
Note : uxunchanged, xxunknown, -xunimplemented, read as "0"
8. Instruction Set :
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t LDWI I SWAPR R, t INCR R, t INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t DECRSZ R, t ANDWR R, t ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR R, t RRR RLR CLRW CLRR BCR BSR R R, b R, b R, t R, t No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return from subroutine Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register Decrement register, skip if zero AND W and register AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear Bit set Function Operating None 0/ WT 0/ WT, stop OSC W/ TMODE Stack/ PC W/ CPIO r W/ R R/ t I/ W [R(0~3) R(4~7)] / t R + 1/ t R + 1/ t W + R/ t R W/ t or (R+/W+1/ t) R 1/ t R 1/ t R a W/ t i a W/ W R a W/ t i a W/ W R o W/ t i o W/ W /R/ t R(n) / R(n-1), C/ R(7), R(0)/ C R(n)/ r(n+1), C/ R(0), R(7)/ C 0/ W 0/ R 0/ R(b) 1/ R(b) Z Z None None C TF, PF TF, PF None None None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C Status
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P.13
2005/5
Ver. 1.9
MDT10P62
Instruction Code 0001bb brrrrrrr 0011bb brrrrrrr 100nnn nnnnnnnn 101nnn nnnnnnnn 110111 iiiiiiii 110001 iiiiiiii 111000 iiiiiiii 010000 00001001 Mnemonic Operands BTSC R, b BTSS R, b LCALL n LJUMP n ADDWI i RTWI i Function Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Add immediate to W Return, place immediate to W Subtract W from immediate Reture from interrupt Operating Skip if R(b)=0 Skip if R(b)=1 n/ PC, PC+1/ Stack n/ PC W+i/ W Stack/ PC,i/ W i-W/ W Stack/ PC,1/ GIS None C,HC,Z None C,HC,Z None Status None None None
SUBWI i RTFI
Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `a ' Exclusive `o ' Logic AND `a ' b t : : 0 1 : : : : : : : : Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
R C HC Z / x i n
9. Electrical Characteristics
*Note: Temperature=25C
1.Absolute maximum rating Maximum current into Vdd pin Maximum current out of Vss pin : 250mA : 300mA
Maximum current sourced by PortA : 150mA Maximum current sourced by PortB : 200mA Maximum current sourced by PortC : 200mA Maximum current sunk by PortA Maximum current sunk by PortB Maximum current sunk by PortC : 150mA : 200mA : 200mA
Maximum output current sourced by any I/O pin : 25mA Maximum output current sunk by any I/O pin These parameters are for reference only. : 25mA
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P.14
2005/5
Ver. 1.9
MDT10P62
2.Operation Current : (1) HF (C=10p) , WDT - enable, PRD - disable SleepAWDT-disableA 4M 2.5V 3.0V 4.0V 5.0V 5.5V 350u 450u 730u 1.1m 1.6m 10M 770u 880u 1.4m 2.0m 2.9m 20M 1.4m 1.7m 2.6m 3.6m 4.8m Sleep 20u 37u 42u 52u 80u PRD-disable 1u 1u 1u 1u 1u
These parameters are for reference only.
(2) XT (C=10p) , WDT - enable, PRD - disable SleepAWDT-disableA 1M 2.5V 3.0V 4.0V 5.0V 5.5V 80u 170u 300u 500u 800u 4M 220u 400u 700u 1.0m 1.4m 10M 500u 850u 1.3m 1.8m 2.7m Sleep 12u 37u 42u 52u 80u PRD-disable 1u 1u 1u 1u 1u
These parameters are for reference only.
(3) LF (C=10p) , WDT - enable, PRD - disable, SleepAWDT-disableA 32K 2.5V 3.0V 4.0V 5.0V 5.5V 25u 35u 50u 100u 200u 455K (2.7V) 80u 100u 140u 200u 300u 1M 100u 130u 190u 250u 350u Sleep 120u 37u 42u 52u 80u PRD-disable 1u 1u 1u 1u 1u
These parameters are for reference only.
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P.15
2005/5
Ver. 1.9
MDT10P62
(4) RC, WDT - enable; PRD - disable; @Vdd = 5.0V SleepAWDT-disableA C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k 4.7k 10k 300p 47k 100k 300k 470k Freq. 12.1M 6.3M 1.4M 702K 235K 149K 5.8M 2.9M 640K 310K 104K 66K 1.7M 865K 190K 91K 31K 19K 740K 362K 79K 38K 13K 8K Current 1.9m 1.1m 350u 220u 140u 130u 1.0m 600u 210u 160u 130u 120u 380u 250u 140u 130u 110u 105u 220u 170u 140u 110u 105u 105u PRD-disable 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u
These parameters are for reference only.
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P.16
2005/5
Ver. 1.9
MDT10P62
RC, WDT - enable; PRD - disable; @Vdd = 3.0V SleepAWDT-disableA C R 4.7k 10k 3p 47k 100k 300k 470k 4.7k 10k 20p 47k 100k 300k 470k 4.7k 10k 100p 47k 100k 300k 470k 4.7k 10k 300p 47k 100k 300k 470k Freq. 11.8M 6.7M 1.7M 900K 275K 176K 6.4M 3.4M 790K 380K 127K 81K 2.2M 1.1M 250K 120K 40K 26K 1.0M 520K 115K 55K 18K 12K Current 1.1m 580u 190u 150u 80u 70u 600u 330u 120u 90u 70u 60u 230u 150u 80u 70u 60u 60u 150u 110u 70u 65u 60u 60u PRD-disable 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u 1u
These parameters are for reference only.
3.Input Voltage (Vdd = 5V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger Min Vss Vss 2.2V 3.8V Max 1.0V 0.6V Vdd Vdd
These parameters are for reference only.
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P.17
2005/5
Ver. 1.9
MDT10P62
Input Voltage (Vdd = 3V) : Port Vil TTL Schmitt trigger Vih TTL Schmitt trigger Min Vss Vss 2.0V 2.6V Max 0.8V 0.4V Vdd Vdd
These parameters are for reference only.
4.Output Voltage (Vdd = 5V) : PA,PB Voh Vol Voh Vol 4.4V 1.2V 4.6V 0.5V Condition Ioh = -20mA Iol = 20mA Ioh = -5mA Iol = 5mA
These parameters are for reference only. Output Voltage (Vdd = 3V) : PA,PB Voh Vol Voh Vol 1.2V 0.6V 2.4V 0.4V Condition Ioh = -20mA Iol = 20mA Ioh = -5mA Iol = 5mA
These parameters are for reference only.
5.The basic WDT time-out cycle time : Time 2.5V 3.0V 4.0V 5.0V 5.5V 25 23 20 17 16 Unit = ms These parameters are for reference only.
6.Temperature & WDT (Vdd = 5V) : Temperature(C) WDT time(ms) -40 12.5 -20 14.2 0 16.1 30 17.5 50 19.5 80 21.7
These parameters are for reference only. This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.18
2005/5
Ver. 1.9
MDT10P62
7.PRD : (1)PRD reset voltage : Voltage Vih Vil 4.010% 3.610% Unit = V These parameters are for reference only. (2) PRD reset current : Current 4.0V 3.6V 100 80 Unit = uA These parameters are for reference only.
8.Pull high resistor : Vdd Pull high 5V 45 3V 85
Unit = K Ohm These parameters are for reference only.
9.MCLR filter time : Vdd=5V Time 720 Unit = ns These parameters are for reference only.
10.OSC1 timing requirements : External clock high or low time (osc1) 2.5us (min) LF mode (1MHz) 80ns (min) XT mode (4MHz) 15ns (min) HF mode (20MHz) External clock rise or fall 50ns (max) LF mode (1MHz) time (osc1) 15ns (max) XT mode (4MHz) 5ns (max) HF mode (20MHz) These parameters are for reference only.
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P.19
2005/5
Ver. 1.9
MDT10P62
11.OSC1 and CLKOUT requirements : OSC1 high to CLKOUT high OSC1 high to CLKOUT low CLKOUT rise time CLKOUT fall time 80ns (typical) RC mode 80ns (typical) RC mode 50ns (typical) RC mode 50ns (typical) RC mode
These parameters are for reference only.
12.OSC1 and PORT OUTPUT requirements : OSC1 high to PORT OUTPUT valid PORT OUTPUT rise time PORT OUTPUT fall time These parameters are for reference only. 100ns (typical) 40ns (typical) 40ns (typical)
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P.20
2005/5
Ver. 1.9
MDT10P62
10. Block Diagram
Stack8 Levels
EPROM 2K (MDT10P62) x14 14 bits
RAM 128X8
P rtA o P 0~ A A P5 its Port A 6b
11 bits 11 bits ProgramCounters
Instruction Register
Special Register P rtB o P 0~ B B P7 Port B 8b its D0~D7
OC S1 OC ML S 2 CR
Oscillator Circuit
Instruction Decoder
Control Circuit PortC
P rtC o P 0~ C C P7 8b its
Data 8-bit Pow onReset er Pow DownReset er P w R g D te to o er an e e c r W orkingRegister A LU StatusRegister
Counter / Tim er0 Tim / Tim er1 er2 (CCP1)
Serial Port (SCM )
W DT/OST Tim er
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.21
2005/5
Ver. 1.9

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